Layout Design Engineering Manager – High Bandwidth Memory

About the role

Micron Technology is seeking a Layout Design Engineering Manager to lead a distributed team within its High Bandwidth Memory (HBM) organization in Guadalajara, Mexico. The manager will oversee the creation of complex analog, mixed‑signal, and custom layouts that enable next‑generation AI and high‑performance computing solutions.

Key responsibilities

• Lead a team responsible for block‑level and full‑chip layout of analog circuits, mixed‑signal components, and custom IP blocks.
• Manage layout verification activities, including LVS, DRC, antenna checks, documentation, and quality reviews.
• Plan, estimate area and timing, schedule, and delegate tasks across multiple concurrent projects.
• Mentor layout engineers at all levels and conduct detailed sub‑block layout reviews.
• Collaborate with global engineering groups to ensure alignment and successful tape‑out delivery.

Required profile

• 15+ years of experience in analog/custom layout design using advanced CMOS nodes (Planar, FinFET).
• 5+ years of experience managing layout engineering teams.
• Strong understanding of matching, electromigration, latch‑up, coupling, crosstalk, IR drop, and parasitic effects.
• Bachelor’s or Master’s degree in Electronics, VLSI Engineering, or related field.

Required skills

• Cadence VLE/VXL
• Mentor Graphics Calibre (DRC/LVS)
• Python, SKILL, Tcl scripting
• Experience with critical IP blocks such as PLL, ADC, DAC, charge pumps, comparators, and differential amplifiers.