Senior Physical Design Engineer - CPU PPA Optimization

About the role

AheadComputing is looking for a Senior Physical Design Engineer to drive CPU power, performance and area (PPA) optimization at advanced technology nodes. The engineer owns the physical implementation of CPU blocks from RTL to GDSII, working with RTL and logic design teams to deliver high-performance, power-efficient processors.

Key responsibilities

• Drive physical implementation of CPU blocks from RTL to GDSII, focusing on PPA trade-offs
• Use back-end EDA tool flows and develop or optimize methodologies for synthesis, place-and-route, clock tree synthesis and timing closure
• Work with RTL designers to improve timing, area and power efficiency, and evaluate design changes against PPA
• Perform static timing analysis, power analysis, signal integrity checks and DFT implementation
• Optimize floorplanning, clock distribution, power delivery networks and congestion reduction strategies
• Automate design flows and methodologies to improve efficiency and scalability

Required profile

• Bachelor's, Master's or PhD in Electrical Engineering, Computer Engineering or a related field
• 4+ years of experience in physical design of complex ASICs or CPUs
• Strong expertise in physical design methodologies, tool flows and PPA trade-offs
• Preferred: experience in advanced process nodes (5nm, 3nm or below)

Required skills

• EDA tools such as Synopsys (ICC2, Design Compiler, PrimeTime) or Cadence (Innovus, Genus, Tempus)
• Place-and-route, clock tree synthesis, timing closure and physical verification
• Power analysis, leakage optimization, ECO implementation and equivalence signoff
• Reading RTL (Verilog/VHDL) and understanding logic design
• Scripting in Python, Tcl or Perl for automation and data analysis
• Preferred: low-power techniques (clock gating, power gating, multi-Vt, multi-power domains), DFT, MCMM constraints and signoff flows

What we offer

• Competitive salary and benefits package
• Professional growth opportunities in an innovative startup environment
• Collaboration with engineers focused on cutting-edge CPU technologies
• A flexible and inclusive work culture based in Guadalajara, Mexico